Altera cyclone V Technical Reference page 119

3-8
Module Reset Signals
Table 3-7: MISC Group, Generated Module Resets
Module Reset Signal
boot_rom_rst_n
onchip_ram_rst_n
sys_manager_rst_n
sys_manager_cold_rst_n
fpga_manager_rst_n
acp_id_mapper_rst_n
h2f_rst_n
h2f_cold_rst_n
rst_pin_rst_n
timestamp_cold_rst_n
clk_manager_cold_rst_n
scan_manager_rst_n
frz_ctrl_cold_rst_n
sys_dbg_rst_n
Altera Corporation
Description
Resets boot ROM
Resets on-chip RAM
Resets system manager
(resets logic associated
with cold or warm reset)
Resets system manager
(resets logic associated
with cold reset only)
Resets FPGA manager
Resets ACP ID mapper
Resets user logic in FPGA
fabric (resets logic
associated with cold or
warm reset)
Resets user logic in FPGA
fabric (resets logic
associated with cold reset
only)
Pulls pin low
nRST
Resets debug timestamp to
0x0
Resets clock manager
(resets logic associated
with cold reset only)
Resets scan manager
Resets freeze controller
(resets logic associated
with cold reset only)
Resets debug masters and
slaves connected to L3
interconnect and level 4
(L4) buses
Reset Cold Warm
Domai Reset Reset
n
Syste X X
m
Syste X X
m
Syste X X
m
Syste X
m
Syste X X
m
Syste X X
m
Syste X X
m
Syste X
m
Syste X
m
Syste X
m
Syste X
m
Syste X X
m
Syste X
m
Syste X X
m
cv_5v4
2016.10.28
Debu Software
g Deassert
Reset
Reset Manager
Send Feedback