Altera cyclone V Technical Reference page 728

10-18
STM Channels
Segment
2
Each of the three masters can access any one of the three address segments. Your software design
determines which master uses which segment, based on the value of bits 24 and 25 in the write address,
AWADDRS[25:24]
Table 10-9: STM AXI Address Fields
STM receives trace data over an AXI slave port. This table contains a list of signals associated with this
interface.
AXI Signal Fields
AWADDRS[7:0]
AWADDRS[23:8]
AWADDRS[25:24]
AWADDRS[31:26]
Each STM message contains a master ID that tells the host debugger which master is associated with the
message. The STM master ID is determined by combining a portion of the
protection bit. In the following table,
Table 10-10: STM Master ID Calculation
Master ID Bits
Master
AWADDRS[29:24]
ID[5:0]
Master
AWPROT[1]
ID[6]
In addition to access through STM channels, the higher-order 28 (31:4) of the 32 event signals are attached
to the FPGA through the FPGA-CTI. These event signals allow the FPGA fabric to send additional
messages using the STM.
Related Information
HPS-FPGA Bridges
•
ARM Infocenter
•
For more information, refer to "System Trace Macrocell" in the Programmers' Model Architecture
Specification .
Altera Corporation
Start Address
0xFE000000
. Software must restrict each master to use only one of the three segments.
These bits index the 256 bytes of the stimulus port.
These bits identify the 65536 stimulus ports associated with a master.
These bits identify the three masters. Only 0, 1, and 2 are valid values.
Always 0x3F. Bits 24 to 31 combine to access 0xFC000000 through
0xFEFFFFFF.
MasterID[6]
AXI Signal Bits
on page 8-1
End Address
0xFEFFFFFF
Description
identifies the
The lowest two bits are sufficient to determine which
master, but CoreSight uses a six-bit master ID.
0 indicates a secure master; 1 indicates a nonsecure
master.
signal and the
AWADDRS
Notes
CoreSight Debug and Trace
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cv_5v4
2016.10.28
AWPROT