Altera cyclone V Technical Reference page 871

13-50
cache_write_enable
copyback_disable Fields
Bit
0
flag
cache_write_enable
Device supports cache write command sequence
Module Instance
nandregs
Offset:
0xA0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
cache_write_enable Fields
Bit
0
flag
cache_read_enable
Device supports cache read command sequence
Module Instance
nandregs
Offset:
0xB0
Altera Corporation
Name
[list][*]1 - Copyback disabled [*]0 - Copyback
enabled[/list]
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
[list][*]1 - Cache write supported [*]0 - Cache write
not supported[/list]
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFB80000
Access
Register Address
0xFFB800A0
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB800B0
NAND Flash Controller
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
1 0
flag
RW 0x0
Reset
RW 0x0
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