Clocks And Resets - Altera cyclone V Technical Reference

Hard processor system

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Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

fn_mod Fields

FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge (lwfpgaslaves) Address Map

This address space is allocated for FPGA-configured slaves driven by the lightweight HPS-to-FPGA bridge

master. Address assignment within this space is user-defined. For more information about Lightweight

HPS-to-FPGA bridges, refer to the HPS-FPGA Bridges chapter of the Hard Processor System Technical

Reference Manual.

Table 8-15: lwfpgaslaves Address Range

Module Instance

LWFPGASLAVES

Clocks and Resets

FPGA-to-HPS Bridge Clocks and Resets

The master interface of the bridge in the HPS logic operates in the

interface exposed to the FPGA fabric operates in the

HPS-FPGA Bridges

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FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge (lwfpgaslaves) Address

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Multiple outstanding write transactions

Only a single outstanding write transaction

Multiple outstanding read transactions

Only a single outstanding read transaction

Start Address

clock domain. The slave

clock domain provided by the user

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