Altera cyclone V Technical Reference page 348

5-154
MIXED2IO3
MIXED2IO3
This register is used to control the peripherals connected to emac1_tx_d3 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x564
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
MIXED2IO3 Fields
Bit
1:0
sel
MIXED2IO4
This register is used to control the peripherals connected to emac1_rx_clk Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x568
Access:
RW
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected emac1_tx_d3. 0 :
Pin is connected to GPIO/LoanIO number 57. 1 : Pin
is connected to Peripheral signal SPIS0.SS0. 2 : Pin is
connected to Peripheral signal SPIM0.SS0. 3 : Pin is
connected to Peripheral signal RGMII1.TXD3.
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFD08000
Register Address
0xFFD08564
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD08568
cv_5v4
2016.10.28
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
System Manager
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