Altera cyclone V Technical Reference page 72

Hard processor system

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Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Clock Manager

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software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

If set to '1', the external regulator is selected for the

PLL. If set to '0', the internal regulator is slected. It is

strongly recommended to select the external regulator

while the PLL is not enabled (in reset), and then

disable the external regulater once the PLL becomes

enabled. Software should simulateously update the

'Enable' bit and the 'External Regulator Input Select'

in the same write access to the VCO register. When

the 'Enable' bit is clear, the 'External Regulator Input

Select' should be set, and vice versa. The reset value of

this bit is applied on a cold reset; warm reset has no

effect on this bit.

Resets the individual PLL output counter. For

software to change the PLL output counter without

producing glitches on the respective clock, SW must

set the VCO register respective Output Counter Reset

bit. Software then polls the respective Output Counter

Reset Acknowledge bit in the Output Counter Reset

Ack Status Register. Software then writes the

appropriate counter register, and then clears the

respective VCO register Output Counter Reset bit.

LSB 'outreset[0]' corresponds to PLL output clock C0,

etc. If set to '1', reset output divider, no clock output

from counter. If set to '0', counter is not reset. The

reset value of this bit is applied on a cold reset; warm

reset has no effect on this bit.

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