Sdram Controller Memory Options - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
DDR PHY
The DDR PHY provides a physical layer interface for read and write memory operations between the
memory controller and memory devices. The DDR PHY has dataflow components, control components,
and calibration logic that handle the calibration for the SDRAM interface timing.
Related Information
Memory Controller Architecture

SDRAM Controller Memory Options

Bank selects, and row and column address lines can be configured to work with SDRAMs of various
technology and density combinations.
Table 11-1: SDRAM Controller Interface Memory Options
Memory Type
(25)
DDR2 1024 (1 Gb)
2048 (2 Gb)
4096 (4 Gb)
1024 (1 Gb)
DDR3
2048 (2 Gb)
4096 (4 Gb)
(25) For all memory types shown in this table, the DQ width is 8.
SDRAM Controller Subsystem
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on page 11-6
Mbits Column
Address Bit
Width
256 10
512 10
10
10
10
512 10
10
10
10
SDRAM Controller Memory Options
Row Address
Bank Select
Bit Width
Bit Width
2 13
2 14
3 14
3 15
3 16
3 13
3 14
3 15
3 16
Page Size MBytes
1024
1024
1024 128
1024 256
1024 512
1024
1024 128
1024 256
1024 512
Altera Corporation
11-3
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