Functional Description Of The Sdram Controller Subsystem - Altera cyclone V Technical Reference

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CSR Interface
CSR Interface
The CSR interface is accessible from the L4 bus. The interface allows code in the HPS MPU or soft IP cores
in the FPGA fabric to configure and monitor the SDRAM controller.
Related Information
Memory Controller Architecture
For more information, refer to the SDRAM Controller Block diagram.

Functional Description of the SDRAM Controller Subsystem

MPFE Operation Ordering
Operation ordering is defined and enforced within a port, but not between ports. All transactions received
on a single port for overlapping addresses execute in order. Requests arriving at different ports have no
guaranteed order of service, except when a first transaction has completed before the second arrives.
Avalon-MM does not support write acknowledgement. When a port is configured to support Avalon-MM,
you should read from the location that was previously written to ensure that the write operation has
completed. When a port is configured to support AXI, the master accessing the port can safely issue a read
operation to the same address as a write operation as soon as the write has been acknowledged. To keep
write latency low, writes are acknowledged as soon as the transaction order is guaranteed—meaning that
any operations received on any port to the same address as the write operation are executed after the write
operation.
To reduce read latency, the single-port logic can return read data out of order to the multi-port logic. The
returned data is rearranged to its initial order on a per port basis by the multi-port logic and no traffic
reordering occurs between individual ports.
Read Data Handling
The MPFE contains a read buffer shared by all ports. If a port is capable of receiving returned data then the
read buffer is bypassed. If the size of a read transaction is smaller than twice the memory interface width,
the buffer RAM cannot be bypassed. The lowest memory latency occurs when the port is ready to receive
data and the full width of the interface is utilized.
MPFE Multi-Port Arbitration
The HPS SDRAM controller multi-port front end (MPFE) contains a programmable arbiter. The arbiter
decides which MPFE port gains access to the single-port memory controller.
The SDRAM transaction size that is arbitrated is a burst of two beats. This burst size ensures that the
arbiter does not favor one port over another when the incoming transaction size is a large burst.
The arbiter makes decisions based on two criteria: priority and weight. The priority is an absolute arbitra‐
tion priority where the higher priority ports always win arbitration over the lower priority ports. Because
multiple ports can be set to the same priority, the weight value refines the port choice by implementing a
round-robin arbitration among ports set to the same priority. This programmable weight allows you to
assign a higher arbitration value to a port in comparison to others such that the highest weighted port
receives more transaction bandwidth than the lower weighted ports of the same priority.
Before arbitration is performed, the MPFE buffers are checked for any incoming transactions. The priority
of each port that has buffered transactions is compared and the highest priority wins. If multiple ports are
of the same highest priority value, the port weight is applied to determine which port wins. Because the
arbiter only allows SDRAM-sized bursts into the single-port memory controller, large transactions may
Altera Corporation
on page 11-6
cv_5v4
2016.10.28
SDRAM Controller Subsystem
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