Altera cyclone V Technical Reference page 785

cv_5v4
2016.10.28
Bit
12
cfg_enable_ecc_code_
overwrites
11
ecccorren
10
eccen
9:8
addrorder
7:3
membl
SDRAM Controller Subsystem
Send Feedback
Name
Set to a one to enable ECC overwrites. ECC
overwrites occur when a correctable ECC error is
seen and cause a new read/modify/write to be
scheduled for that location to clear the ECC error.
Enable auto correction of the read data returned
when single bit error is detected.
Enable the generation and checking of ECC. This bit
must only be set if the memory connected to the
SDRAM interface is 24 or 40 bits wide. If you set this,
you must clear the useeccasdata field in the staticcfg
register.
This bit field selects the order for address interleaving.
Programming this field with different values gives
different mappings between the AXI or Avalon-MM
address and the SDRAM address. Program this field
with the following binary values to select the
ordering.
Value
0x0
0x1
0x2
0x3
Altera recommends programming addrorder to 0x0
or 0x2.
Configures burst length as a static decimal value.
Legal values are valid for JEDEC allowed DRAM
values for the DRAM selected in cfg_type. For DDR3,
this should be programmed with 8 (binary "01000"),
for DDR2 it can be either 4 or 8 depending on the
exact DRAM chip. LPDDR2 can be programmed with
4, 8, or 16 and LPDDR can be programmed with 2, 4,
or 8. You must also program the membl field in the
staticcfg register.
Description
Description Address Interleaving
chip, row, bank, Bank interleaved with no
column rank (chip select)
interleaving
chip, bank, row, No interleaving
column
row, chip, bank, Bank interleaved with
column rank (chip select)
interleaving
reserved N/A
11-47
ctrlcfg
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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