Altera cyclone V Technical Reference page 480

7-32
remap
Register
write_qos on page 7-
125
fn_mod on page 7-126
NAND
Register
read_qos on page 7-
127
write_qos on page 7-
128
fn_mod on page 7-129
USB1
Register
fn_mod_ahb on page 7-
130
read_qos on page 7-
131
write_qos on page 7-
132
fn_mod on page 7-133
remap
The L3 interconnect has separate address maps for the various L3 Masters. Generally, the addresses are the
same for most masters. However, the sparse interconnect of the L3 switch causes some masters to have
holes in their memory maps. The remap bits are not mutually exclusive. Each bit can be set independently
and in combinations. Priority for the bits is determined by the bit offset: lower offset bits take precedence
over higher offset bits.
Module Instance
l3regs
Altera Corporation
Offset Width Acces
s
0x4A104 32 RW
0x4A108 32 RW
Offset Width Acces
s
0x4B100 32 RW
0x4B104 32 RW
0x4B108 32 RW
Offset Width Acces
s
0x4C028 32 RW
0x4C100 32 RW
0x4C104 32 RW
0x4C108 32 RW
Base Address
0xFF800000
Reset Value
Write Channel QoS Value
0x0
Issuing Functionality Modification
0x0
Register
Reset Value
Read Channel QoS Value
0x0
Write Channel QoS Value
0x0
Issuing Functionality Modification
0x0
Register
Reset Value
Functionality Modification AHB
0x0
Register
Read Channel QoS Value
0x0
Write Channel QoS Value
0x0
Issuing Functionality Modification
0x0
Register
Register Address
0xFF800000
cv_5v4
2016.10.28
Description
Description
Description
System Interconnect
Send Feedback