Altera cyclone V Technical Reference page 577

Hard processor system
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cv_5v4
2016.10.28
fn_mod
Sets the block issuing capability to multiple or single outstanding transactions.
Module Instance
l3regs
Offset:
0x4B108
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
fn_mod Fields
Bit
1
wr
0
rd
USB1 Register Descriptions
Registers associated with the USB1 slave interface. This slave is used by the DMA controller built into the
USB1 to access slaves attached to the L3/L4 Interconnect.
Offset:
0xa000
fn_mod_ahb
Controls how AHB-lite burst transactions are converted to AXI tranactions.
System Interconnect
Send Feedback
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Name
Value
0x0
0x1
Value
0x0
0x1
on page 7-130
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Reserved
Description
Description
Multiple outstanding write transactions
Only a single outstanding write transaction
Description
Multiple outstanding read transactions
Only a single outstanding read transaction
fn_mod
Register Address
0xFF84B108
21
20
19
18
5
4
3
2
Access
7-129
17
16
1
0
wr
rd
RW
RW 0x0
0x0
Reset
RW
0x0
RW
0x0
Altera Corporation

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