Altera cyclone V Technical Reference page 161

4-18
dclkcnt
Bit
2
nconfigpull
1
nce
0
en
dclkcnt
Used to give software control in enabling DCLK at any time. SW will need control of the DCLK in specific
configuration and partial reconfiguration initialization steps to send spurious DCLKs required by the CB.
SW takes ownership for DCLK during normal configuration, partial reconfiguration, error scenerio
handshakes including SEU CRC error during partial reconfiguration, SW early abort of partial
reconfiguration, and initializatin phase DCLK driving. During initialization phase, a configuration image
loaded into the FPGA can request that DCLK be used as the initialization phase clock instead of the
default internal oscillator or optionally the CLKUSR pin. In the case that DCLK is requested, the
DCLKCNT register is used by software to control DCLK during the initialization phase. Software should
poll the DCLKSTAT.DCNTDONE write one to clear register to be set when the correct number of DCLKs
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The nCONFIG input is used to put the FPGA into its
reset phase. If the FPGA was configured, its operation
stops and it will have to be configured again to start
operation.
Value
0x0
0x1
This field drives the active-low Chip Enable (nCE)
signal to the CB. It should be set to 0 (configuration
enabled) before CTRL.EN is set. This field only effects
the FPGA if CTRL.EN is 1.
Value
0x0
0x1
Controls whether the FPGA configuration pins or
HPS FPGA Manager drive configuration inputs to the
CB.
Value
0x0
0x1
Description
Description
Don't pull-down nCONFIG input to the CB.
Pull-down nCONFIG input to the CB. This
puts the FPGA in reset phase and restarts
configuration.
Description
Configuration is enabled. The nCE to the CB
is driven to 0.
Configuration is disabled. The nCE to the CB
is driven to 1.
Description
FPGA configuration pins drive configuration
inputs to the CB. Used when FPGA is
configured by means other than the HPS.
FPGA Manager drives configuration inputs
to the CB. Used when HPS configures the
FPGA.
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
FPGA Manager
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