Communicating With The Jtag Tap Controller - Altera cyclone V Technical Reference

6-6

Communicating with the JTAG TAP Controller

Communicating with the JTAG TAP Controller
After the system manager undergoes a cold reset, access to the JTAG TAP controller in the FPGA control
block is through the dedicated FPGA JTAG I/O pins. If necessary, you can configure your system to use
the scan manager to provide the HPS processor access to the JTAG TAP controller, instead. This feature
allows the processor to send JTAG instructions to the FPGA portion of the device.
To connect scan chain 7 between the scan manager and the FPGA JTAG TAP controller, the following
features must be enabled:
• The scan chain for the FPGA JTAG TAP controller—To enable scan chain 7, set the
the register in the scan manager. For more information, refer to "Scan Manager Address Map and
en
Register Definitions".
• The FPGA JTAG logic source select—This source select determines whether the scan manager or the
dedicated FPGA JTAG pins are connected to the FPGA JTAG TAP controller in the FPGA portion of
the device. On system manager cold reset, the dedicated FPGA JTAG pins are selected. The source
select is configured through the
system manager. The FPGA JTAG pins and scan manager connection to the TAP controller must both
be inactive when switching between them. The mechanism to ensure both are inactive is user-defined.
Note: Before connecting or disconnecting the scan chain between the scan manager and the FPGA JTAG
TAP controller, ensure that both the FPGA JTAG
Altera recommends resetting the FPGA JTAG TAP controller using the scan manager's
signal after the scan manager is connected to the controller.
Related Information
• en on page 6-11
Information about configuring the scan manager's en register
Scan Manager Address Map and Register Definitions
•
• System Manager
For information about the system manager, including details about configuring the
to the System Manager chapter.
JTAG-AP FIFO Buffer Access and Byte Command Protocol
The JTAG-AP contains FIFO buffers for byte commands and responses. The buffers are accessed through
the
fifosinglebyte
stalls processor access to the registers when the buffer does not contain enough data for read access, or
when the buffer does not contain enough free space to accept data for write access.
Note: Software should read the
status before performing the access to avoid being stalled by the JTAG-AP.
JTAG-AP scan chains 0, 1, 2 and 3 are write-only ports connected to the HPS IOCSRs and JTAG-AP scan
chain 7 is a read-write port connected to the FPGA JTAG TAP controller. The processor can send data to
scan chains 0-3, and send and receive data from scan chain 7 by accessing the command and response
FIFO buffers in the JTAG-AP.
Note: Attempting to access data at invalid or non-aligned offsets can produce unpredictable results that
require a reset to recover.
Altera Corporation
fpgajtagen
on page 5-1
, ,
fifodoublebyte fifotriplebyte
and
rfifocnt
bit of the register in the
ctrl
and scan manager
TCK
on page 6-8
, and
fifoquadbyte
fields of the
wfifocnt stat
field of
fpgajtag
group of the
scanmgrgrp
signals are de-asserted.
TCK
nTRST
register, refer
ctrl
registers. The JTAG-AP
register to determine the buffer
Scan Manager
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cv_5v4
2016.10.28