Altera cyclone V Technical Reference page 671

cv_5v4
2016.10.28
Interconnect
Master
EMAC0
EMAC1
USB0
USB1
NAND
ETR
(23) Values are in binary. The letter
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
(23)
ID
When
1000 0000 x001
EMAC0 Rx channel is accessing
memory and when
indicates the EMAC0 Tx channel is
accessing memory.
Each channel, Rx and Tx, requires
read access to memory. This
requirement exists because each
channel DMA controller reads
descriptors from memory when the
packet is moved to or from
memory. If you use static ACP ID
mapping, you must allocate two
static mappings for EMAC0: one
for
x=0
When
1000 0000 x010
EMAC1 Rx channel is accessing
memory and when
indicates the EMAC1 Tx channel is
accessing memory.
Each channel, Rx and Tx, requires
read access to memory. This
requirement exists because each
channel DMA controller reads
descriptors from memory when the
packet is moved to or from
memory. If you use static ACP ID
mapping, then you must allocate
two static mappings for EMAC1:
one for
1000 0000 0011 1000 0000 0011
1000 0000 0110 1000 0000 0110
1000 0000 0100 1000 0000 0100
1000 0000 0000 1000 0000 0000
denotes variable ID bits that each master passes with each transaction.
x
vid*rd.mid
, this indicates the
x=0
, this
x=1
and one for .
x=1
, this indicates the
x=0
, this
x=1
and one for .
x=0 x=1
HPS Peripheral Master Input IDs
vid*wr.mid
When , this indicates the
x=0
EMAC0 Rx channel is accessing
memory and when
x=1
indicates the EMAC0 Tx
channel is accessing memory.
Each channel, Rx and Tx,
requires write access to
memory. This requirement
exists because each channel
DMA controller writes descrip‐
tors to memory when the
packet is moved to or from
memory. If you use static ACP
ID mapping, then you need to
allocate two static mappings for
EMAC0: one for
x=0
for .
x=1
When , this indicates the
x=0
EMAC1 Rx channel is accessing
memory and when
x=1
indicates the EMAC1 Tx
channel is accessing memory.
Each channel, Rx and Tx,
requires write access to
memory. This requirement
exists because each channel
DMA controller writes descrip‐
tors to memory when the
packet is moved to or from
memory. If you use static ACP
ID mapping, then you must
allocate two static mappings for
EMAC1: one for
x=0
for .
x=1
1000 0000 0011
1000 0000 0110
1000 0000 0100
1000 0000 0000
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9-35
, this
and one
, this
and one