L4 Peripheral Clocks - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
f2h_sdram_ref_clk
HPS_CLK2
HPS_CLK1
Reset
reset_manager_safe_mode_req
Manager

L4 Peripheral Clocks

The L4 peripheral clocks, denoted by
Table 2-1: Clock List
Peripheral
USB OTG 0/1
(6)
Clock Manager
Send Feedback
f2h_periph_ref_clk
Main Clock Group
Main
Dividers
PLL 0
Peripheral Clock Group
Peripheral
Dividers
PLL 1
SDRAM Clock Group
SDRAM
PLL
OSC1 Clock Group
Control
Logic
l4_mp_clk
Clock Name
hclk
pmu_hclk
utmi_clk
FPGA Portion
Clock Manager
osc1_clk
Control & Status
Registers
L4 Bus (osc1_clk)
, range up to 200 MHz.
AHB clock
PMU AHB clock.
clock for the PMU's AHB domain.
Note: Select it as a test clock.
Always used as the PHY domain clock
during DFT Scan mode.
Note: Select
even when the core is configured
for a non-UTMI PHY.
L4 Peripheral Clocks
Flash Controller C locks
Divider
Description
is the scan
pmu_hclk
as a test clock
utmi_clk
Altera Corporation
2-3
Flash
Controllers
MPU, L3, L4
& Debug
PLL-Driven
Peripherals
SDRAM
Controller
Subsystem
OSC1-Driven
Peripherals