Altera cyclone V Technical Reference page 59

2-22
Clock Usage By Module
Module Name
CAN controller 0
CAN controller 1
GPIO interface 0
GPIO interface 1
GPIO interface 2
System manager
SDRAM subsystem
L4 watchdog timer 0
Altera Corporation
System Clock Name
l4_sp_clk
can0_clk
l4_sp_clk
can1_clk
l4_mp_clk
gpio_db_clk
l4_mp_clk
gpio_db_clk
l4_mp_clk
gpio_db_clk
osc1_clk
l4_sp_clk
ddr_dq_clk
ddr_dqs_clk
ddr_2x_dqs_clk
mpu_l2_ram_clk
l3_main_clk
osc1_clk
Use
Slave
CAN 0 controller
Slave
CAN 1 controller
Slave
Debounce
Slave
Debounce
Slave
Debounce
System manager
Control slave
Off-chip data
MPFE, single-port controller,
CSRs, and PHY
Off-chip strobe data
Slave connected to MPU
subsystem L2 cache
Slave connected to L3 intercon‐
nect
L4 watchdog timer 0
Send Feedback
cv_5v4
2016.10.28
Clock Manager