Hps External Reset Sources - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Figure 3-1: Reset Manager Block Diagram
FPGA Portion
HPS
Scan Manager
nPOR
nRST
POR Voltage
Detector
Watchdog (2)

HPS External Reset Sources

The following table lists the reset sources external to the HPS. All signals are synchronous to the
clock. The reset signals from the HPS to the FPGA fabric must be synchronized to your user logic clock
domain.
Reset Manager
Send Feedback
Control
Block
load_csr usermode
Scan Manager Reset Request
Watchdog Reset Request[1:0]
MPU
Debug Reset Request
DAP
POR Voltage Reset Request
System Watchdog Reset Request[1:0]
HPS External Reset Sources
FPGA Fabric
f2h_dbg_rst_req_n
h2f_dbg_rst_n
f2h_cold_rst_req_n
f2h_warm_rst_req_n
h2f_cold_rst_n
Reset Manager
fpga_config_complete
Reset
Controller
(swcoldrstreq and
swwarmrstreq bits of ctrl)
CSRs
Slave Interface
L4 Peripheral Bus (osc1_clk)
h2f_rst_n
Signal
Assertion /
De-Assertion
(mpumodrst,
permodrst,
per2modrst,
brgmodrst,
and
miscmodrst)
osc1_clk
Altera Corporation
3-3
HPS
Modules
Module
Reset
Signals