Altera cyclone V Technical Reference page 537

cv_5v4
2016.10.28
31 30
15 14
fn_mod Fields
Bit
1
wr
0
rd
HPS2FPGA Register Descriptions
Registers associated with the HPS2FPGA AXI Bridge master. This master is used to access the HPS2FPGA
AXI Bridge slave. This slave is used to access slaves in the FPGA connected to the HPS2FPGA AXI Bridge.
Offset:
0x22000
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
wr_tidemark
Controls the release of the transaction in the write data FIFO.
fn_mod
on page 7-91
Sets the block issuing capability to multiple or single outstanding transactions.
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
Module Instance
l3regs
System Interconnect
Send Feedback
29 28 27 26
13 12 11 10
Name
Value
0x0
0x1
Value
0x0
0x1
on page 7-89
on page 7-90
0xFF800000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Multiple outstanding write transactions
Only a single outstanding write transaction
Description
Multiple outstanding read transactions
Only a single outstanding read transaction
Base Address
HPS2FPGA Register Descriptions
21 20 19 18
5 4 3 2
Access
Register Address
0xFF824008
7-89
17 16
1 0
wr rd
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
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