Altera cyclone V Technical Reference page 179

4-36
gpio_intstatus
Bit
1
cd
0
ns
gpio_intstatus
Reports on interrupt status for each GPIO input. The interrupt status includes the effects of masking.
Module Instance
fpgamgrregs
Offset:
0x840
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
Altera Corporation
Name
Controls the polarity of edge or level sensitivity for
CONF_DONE
0x0
0x1
Controls the polarity of edge or level sensitivity for
nSTATUS
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
fpo cdp
RO RO
0x0 0x0
Description
Value
Active low
Active high
Value
Active low
Active high
Base Address
0xFF706000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
nsp ncp prd pre
RO RO RO RO
0x0 0x0 0x0 0x0
Description
Description
Register Address
0xFF706840
21 20 19 18
5 4 3
prr ccd crc id
RO RO RO RO
0x0 0x0 0x0 0x0
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
17 16
2 1 0
cd ns
RO RO 0x0
0x0
FPGA Manager
Send Feedback