Altera cyclone V Technical Reference page 188

cv_5v4
2016.10.28
gpio_ext_porta Fields
Bit
11
fpo
10
cdp
9
nsp
8
ncp
7
prd
6
pre
5
prr
4
ccd
3
crc
2
id
1
cd
0
ns
gpio_ls_sync
The Synchronization level register is used to synchronize inputs to the l4_mp_clk. All MON interrupts are
already synchronized before the GPIO instance so it is not necessary to setup this register to enable
synchronization.
Module Instance
fpgamgrregs
Offset:
0x860
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
FPGA Manager
Send Feedback
Name
Reading this provides the value of FPGA_POWER_
ON
Reading this provides the value of CONF_DONE Pin
Reading this provides the value of nSTATUS Pin
Reading this provides the value of nCONFIG Pin
Reading this provides the value of PR_DONE
Reading this provides the value of PR_ERROR
Reading this provides the value of PR_READY
Reading this provides the value of CVP_CONF_
DONE
Reading this provides the value of CRC_ERROR
Reading this provides the value of INIT_DONE
Reading this provides the value of CONF_DONE
Reading this provides the value of nSTATUS
0xFF706000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Base Address
0xFF706860
4-45
gpio_ls_sync
Access Reset
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
Register Address
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