Reset Sequencing - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
If a cold reset request is issued while another cold reset is already underway, the reset manager extends the
reset period for all the module reset outputs until all cold reset requests are removed. If a cold reset request
is issued while the reset manager is removing other modules out of the reset state, the reset manager
returns those modules back to the reset state.
If a warm reset request is issued while another warm reset is already underway, the first warm reset
completes before the second warm reset begins. If the second warm reset request is removed before the
first warm reset completes, the warm first reset is extended to meet the timing requirements of the second
warm reset request.
The pin can be used to extend the cold reset beyond what the POR voltage monitor automatically
nPOR
provides. The use of the
Related Information
Cyclone V Device Datasheet
For information about the required duration of reset request signal assertion, refer to the Cyclone V
Device Datasheet.

Reset Sequencing

The reset controller sequences resets without software assistance. Module reset signals are asserted
asynchronously and synchronously. The reset manager deasserts the module reset signals synchronous to
the
osc1_clk
signals in a group are deasserted at the same time.
The reset manager sends a safe mode request to the clock manager to put the clock manager in safe mode,
which creates a fixed and known relationship between the
by the clock manager.
After the reset manager releases the MPU subsystem from reset, CPU1 is left in reset and CPU0 begins
executing code from the reset vector address. Software is responsible for deasserting CPU1 and other
resets, as shown in the MPU Group and Generated Module Resets table. Software deasserts resets by
writing the
registers.
Software can also bypass the reset controller and generate reset signals directly through the module-reset
control registers. In this case, software is responsible for asserting module reset signals, driving them for
the appropriate duration, and deasserting them in the correct order. The clock manager is not typically in
safe mode during this time, so software is responsible for knowing the relationship between the clocks
generated by the clock manager. Software must not assert a module reset signal that would prevent
software from deasserting the module reset signal. For example, software should not assert the module
reset to the processor executing the software.
Table 3-10: Minimum Pulse Width
Warm Reset
Cold Reset
Reset Manager
Send Feedback
pin is optional and can be tied high when it is not required.
nPOR
clock. Module reset signals are deasserted in groups in a fixed sequence. All module reset
, ,
mpumodrst permodrst per2modrst
Reset Type
clock and all other clocks generated
osc1_clk
, , and
brgmodrst miscmodrst
6 cycles
osc1_clk
6 cycles
osc1_clk
Reset Sequencing
module-reset control
Value
Altera Corporation
3-11