Altera cyclone V Technical Reference page 685

cv_5v4
2016.10.28
31 30
15 14
Reserved
dynrd Fields
Bit
13:12
page
8:4
user
dynwr
The Write AXI Master Mapping Register contains the USER, and ADDR page signals mapping values for
transaction that dynamically remapped to one of the available 3-bit virtual IDs.
Module Instance
acpidmap
Offset:
0x2C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
29 28 27 26
13 12 11 10
page Reserved
RW 0x0
Name
ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory
region.
This value is propagated to SCU as ARUSERS.
0xFF707000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
page Reserved
RW 0x0
Bit Fields
25 24 23 22
Reserved
9 8 7 6
user
RW 0x0
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
user
RW 0x0
dynwr
21 20 19 18
5 4 3 2
Reserved
Access
Register Address
0xFF70702C
21 20 19 18
5 4 3 2
Reserved
9-49
17 16
1 0
Reset
RW 0x0
RW 0x0
17 16
1 0
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