Controller/Dma/Fifo Buffer Reset Usage - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
You can also use the
sdmmc_cclk_out
Related Information
Interrupt and Error Handling
Refer to this section for information about hardware lock errors.

Controller/DMA/FIFO Buffer Reset Usage

The following list shows the effect of reset on various parts in the SD/MMC controller:
• Controller reset—resets the controller by setting the
Controller reset resets the CIU and state machines, and also resets the BIU-to-CIU interface. Because
this reset bit is self-clearing, after issuing the reset, wait until this bit changes to 0.
• FIFO buffer reset—resets the FIFO buffer by setting the FIFO reset bit (
register to 1. FIFO buffer reset resets the FIFO buffer pointers and counters in the FIFO buffer. Because
this reset bit is self-clearing, after issuing the reset, wait until this bit changes to 0.
• DMA reset—resets the internal DMA controller logic by setting the DMA reset bit (
register to 1, which immediately terminates any DMA transfer in progress. Because this reset bit
ctrl
is self-clearing, after issuing the reset, wait until this bit changes to 0.
Note: Ensure that the DMA is idle before performing a DMA reset. Otherwise, the L3 interconnect might
be left in an indeterminate state.
Altera recommends setting the
to 1 first, and then resetting the
Enabling FIFO Buffer ECC
To protect the FIFO buffer data with ECC, you must enable the ECC feature before performing any
operations with the SD/MMC controller. Perform the following steps to enable the FIFO buffer ECC
feature:
1. Verify there are no commands committed to the controller.
2. Ensure that the FIFO buffer is initialized. Initialize the FIFO buffer by writing 0 to all 1024 FIFO buffer
locations. A FIFO buffer write to any address from 0x200 to the maximum FIFO buffer size is valid.
3. Set the SDMMC RAM ECC single and double, correctable error interrupt status bits (
derrporta
manager, to clear any previously-detected ECC errors.
4. Reset the FIFO buffer by setting the
and counters in the FIFO buffer. This reset bit is self-clearing, so after issuing the reset, wait until the bit
changes to 0.
5. Set the
en
FIFO buffer in SD/MMC controller.
Non-Data Transfer Commands
To send any non-data transfer command, the software needs to write the
register with appropriate parameters. Using these two registers, the controller forms the command and
sends it to the
the
rintsts
When a response is received—either erroneous or valid—the controller sets the
register to 1. A short response is copied to
rintsts
SD/MMC Controller
Send Feedback
register to enable low-power mode, which automatically stops the
clkena
clock when the card is idle for more than eight clock cycles.
on page 14-73
controller_reset
rintsts
, , and
serrportb derrportb
bit in register in
sdmmc eccgrp
pin. The controller reports errors in the command response through the error bits of
CMD
†
register.
Controller/DMA/FIFO Buffer Reset Usage
controller_reset
†
,
fifo_reset
register to 0 using another write, to clear any resultant interrupt.
) to 1 in the register in the
sdmmc
bit to 1 in the
fifo_reset
group of the system manager to 1, to enable ECC for the
, while a long response is copied to all four
resp0
†
bit in the
ctrl
†
) in the
fifo_reset
†
dma_reset
†
, and bits in the
dma_reset
serrporta
group of the system
eccgrp
register. This action resets pointers
ctrl
register and the
cmd
command_done
14-47
register to 1.
ctrl
) in the
register
ctrl
,
cmdarg
bit in the
Altera Corporation