Altera cyclone V Technical Reference page 63

2-26
ctrl
SDRAM PLL Group
Register
vco on page 2-64
ctrl on page 2-66
ddrdqsclk on page 2-
67
ddr2xdqsclk
2-68
ddrdqclk on page 2-
69
s2fuser2clk
2-70
en on page 2-71
stat on page 2-72
ctrl
Contains fields that control the entire Clock Manager.
Module Instance
clkmgr
Offset:
0x0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Offset
0xC0
0xC4
0xC8
on page 0xCC
0xD0
on page 0xD4
0xD8
0xDC
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Width Acces Reset Value
s
32 RW 0x8001000D
32 RW 0x4002
32 RW 0x1
32 RW 0x1
32 RW 0x1
32 RW 0x1
32 RW 0xF
32 RO 0x0
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
SDRAM PLL VCO Control
Register
SDRAM PLL VCO Advanced
Control Register
SDRAM PLL C0 Control Register
for Clock ddr_dqs_clk
SDRAM PLL C1 Control Register
for Clock ddr_2x_dqs_clk
SDRAM PLL C2 Control Register
for Clock ddr_dq_clk
SDRAM PLL C5 Control Register
for Clock s2f_user2_clk
Enable Register
SDRAM PLL Output Counter
Reset Ack Status Register
Register Address
0xFFD04000
21 20 19 18
5 4 3 2
ensfm
dwr
RW
0x1
cv_5v4
2016.10.28
17 16
1 0
Reser safemode
ved
RW 0x1
Clock Manager
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