Altera cyclone V Technical Reference page 584

8-2
Features of the HPS-FPGA Bridges
Implements clock crossing and manages the
transfer of data across the clock domains in the
HPS logic and the FPGA fabric
Performs data width conversion between the HPS
logic and the FPGA fabric
Allows configuration of FPGA interface widths at
instantiation time
Each bridge consists of a master-slave pair with one interface exposed to the FPGA fabric and the other
exposed to the HPS logic. The FPGA-to-HPS bridge exposes an AXI slave interface that you can connect
to AXI master or Avalon-MM interfaces in the FPGA fabric. The HPS-to-FPGA and lightweight HPS-to-
FPGA bridges expose an AXI master interface that you can connect to AXI or Avalon-MM slave interfaces
in the FPGA fabric.
Related Information
AXI Bridges
Information about configuring the AXI bridges
Altera Corporation
Feature
on page 27-7
FPGA-to-HPS HPS-to-FPGA
Bridge Bridge
Y Y
Y Y
Y Y
cv_5v4
2016.10.28
Lightweight HPS-to-
FPGA Bridge
Y
Y
N
HPS-FPGA Bridges
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