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Cyclone IV GX Transceiver Starter Board Reference Manual 101 Innovation Drive Document Version: San Jose, CA 95134 Document Date: March 2010 www.altera.com Downloaded from Elcodis.com electronic components distributor...
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Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation.
FPGA designs that interface with all components of the board. General Description The Cyclone IV GX transceiver starter board provides a hardware platform for developing and prototyping low-power, high-volume, feature-rich designs as well as to demonstrate the Cyclone IV GX device's on-chip memory, embedded multipliers, and the Nios ®...
1–2 Chapter 1: Overview Board Component Blocks Board Component Blocks The board features the following major component blocks: ■ Cyclone IV GX EP4CGX15BF14 FPGA in the 169-pin FineLine BGA (FBGA) package 14,400 LEs ■ 540-kilobit (Kb) on-die memory ■ 20 global clocks ■...
A complete set of schematics, a physical layout database, and GERBER files for the starter board reside in the Cyclone IV GX Transceiver starter kit documents directory. For information about powering up the board and installing the demonstration...
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(C58, C59) Connector Connectors (U14) (J10, J11) Table 2–1 describes the components and lists their corresponding board references. Table 2–1. Cyclone IV GX Transceiver Starter Board Components (Part 1 of 3) Board Reference Type Description Featured Devices FPGA EP4CGX15BF14, 169-pin FBGA.
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Chapter 2: Board Components 2–3 Board Overview Table 2–1. Cyclone IV GX Transceiver Starter Board Components (Part 2 of 3) Board Reference Type Description Load LED Illuminates when the MAX II CPLD EPM2210 System Controller is actively configuring the FPGA.
2–4 Chapter 2: Board Components Featured Device: Cyclone IV GX Device Table 2–1. Cyclone IV GX Transceiver Starter Board Components (Part 3 of 3) Board Reference Type Description J8, J9 Transceiver RX SMA connectors Two input SMAs (optional) to the high-speed positive and negative differential receiver channel.
Bank 5A Bank Name Number of I/Os Table 2–4 lists the Cyclone IV GX device pin count and usage by function on the starter board. Table 2–4. Cyclone IV GX Device I/O Pin Count and Usage (Note 1) Function I/O Standard...
2–6 Chapter 2: Board Components MAX II CPLD EPM2210 System Controller MAX II CPLD EPM2210 System Controller The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the following purposes: ■ FPGA configuration from flash memory ■...
The USB-Blaster is implemented using a USB Type-B connector (J5), a FTDI USB 2.0 PHY device (U5), and an Altera MAX II CPLD (U4). This allows the configuration of the FPGA using a USB cable directly connected between the USB port on the board (J5) and a USB port of a PC running the Quartus II software.
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JTAG 2 x 5 Header The Cyclone IV GX FPGA is configured via JTAG using the MAX II configuration controller design (embedded blaster) as the primary configuration mode. The board includes a MAX II CPLD EPM2210 System Controller which interfaces directly to the Cyclone IV GX FPGA for configuration, LCD control, power monitor control, and other purposes.
The secondary method is to use the pre-built parallel flash loader (PFL) design included in the starter kit. The starter board implements the Altera PFL megafunction for flash memory programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD).
EPCS device is to use the Serial FlashLoader (SFL), a JTAG-based in-system programming solution for Altera serial configuration devices. The SFL is a bridge design for the FPGA that uses the JTAG connector (J1) to access the JTAG Indirect Configuration Device Programming File (.jic) and then uses the AS interface to...
Board references S5 and S6 are push-button switches that allow you to interact with the Cyclone IV GX device. When the switch is pressed and held down, the device pin is set to logic 0; when the switch is released, the device pin is set to logic 1. There is no board-specific function for these general user push-button switches.
The starter board comes with a full height I/O bracket for its low profile form factor card. This interface uses the Cyclone IV GX device's PCI Express hard IP block, saving logic resources for the user logic application.
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PC motherboard on this board through the PCI Express edge connector. This signal connects directly to a Cyclone IV GX REFCLK input pin pair. This clock is terminated on the motherboard and therefore, no on-board termination is required.
The MAC function must be provided in the FPGA for typical networking applications such the Altera Triple Speed Ethernet MegaCore design. The Marvell 88E1111 PHY uses 2.5-V and 1.2-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator.
8-channel differential input 24-bit ADC device to measure voltage and current. A SPI bus connects the ADC device to the MAX II CPLD EPM2210 System Controller as well as the Cyclone IV GX Transceiver. Figure 2–8 shows the block diagram for the power measurement circuitry.
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