Altera cyclone V Technical Reference page 273

cv_5v4
2016.10.28
Module Instance
sysmgr
Offset:
0x150
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
emac0 Fields
Bit
8
rxfifoderr
7
rxfifoserr
6
txfifoderr
5
txfifoserr
System Manager
Send Feedback
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
This bit is an interrupt status bit for EMAC0 RXFIFO
RAM ECC double bit, non-correctable error. It is set
by hardware when double bit, non-correctable error
occurs in EMAC0 RXFIFO RAM. Software needs to
write 1 into this bit to clear the interrupt status.
This bit is an interrupt status bit for EMAC0 RXFIFO
RAM ECC single, correctable error. It is set by
hardware when single, correctable error occurs in
EMAC0 RXFIFO RAM. Software needs to write 1
into this bit to clear the interrupt status.
This bit is an interrupt status bit for EMAC0 TXFIFO
RAM ECC double bit, non-correctable error. It is set
by hardware when double bit, non-correctable error
occurs in EMAC0 TXFIFO RAM. Software needs to
write 1 into this bit to clear the interrupt status.
This bit is an interrupt status bit for EMAC0 TXFIFO
RAM ECC single, correctable error. It is set by
hardware when single, correctable error occurs in
EMAC0 TXFIFO RAM. Software needs to write 1
into this bit to clear the interrupt status.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
rxfif rxfif txfif
oderr oserr oderr
RW RW RW
0x0 0x0 0x0
Description
Register Address
0xFFD08150
21 20 19 18
5 4 3 2
txfif rxfif rxfif txfif
oserr oinjd oinjs oinjd
RW RW RW RW
0x0 0x0 0x0 0x0
Access
5-79
emac0
17 16
1 0
txfif en
oinjs
RW 0x0
RW
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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