Snoop Control Unit - Altera cyclone V Technical Reference

9-26

Snoop Control Unit

Snoop Control Unit
The SCU manages data traffic for the Cortex-A9 processors and the memory system, including the L2
cache. In a multi-master system, the processors and other masters can operate on shared data. The SCU
ensures that each processor operates on the most up-to-date copy of data, maintaining cache coherency.
Functional Description
The SCU is used to connect the Cortex-A9 processors and the ACP to the L2 cache controller. The SCU
performs the following functions:
• When the processors are set to SMP mode, the SCU maintains data cache coherency between the
processors.
Note: The SCU does not maintain coherency of the instruction caches.
• Initiates L2 cache memory accesses
• Arbitrates between processors requesting L2 access
• Manages ACP access with cache coherency capabilities.
Related Information
ARM Infocenter
For more information about the SCU, refer to the Snoop Control Unit chapter of the Cortex-A9 MPCore
Technical Reference Manual, available on the ARM Infocenter website.
Coherent Memory, Snoop Control Unit, and Accelerator Coherency Port
Figure 9-3: Data Flow Between L1 Caches and SCU
This diagram illustrates the flow of data among the L1 data caches and the SCU.
HPS
Mastering
Peripherals
Related Information
Accelerator Coherency Port
Altera Corporation
FPGA Fabric
Accelerator
System
Coherency
Interconnect
Port (ACP)
on page 9-27
ARM Cortex-A9
32-Bit Dual-Issue
Superscalar
RISC Processor
L1 Data
32 KB
Cache
Instruction
Cache
S noop C o n t r ol Unit (SCU)
Level 2 (L2) Unified Cache
Unidirectional
Coherency
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
ARM Cortex-A9
32-Bit Dual-Issue
Superscalar
RISC Processor
L1 Data
32 KB
Cache
Instruction
Cache
Bidirectional Coherent
Coherency Memory
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