Document Revision History - Altera cyclone V Technical Reference

3-32

Document Revision History

tstscratch Fields
Bit
31:0
field0
Document Revision History
Table 3-11: Document Revision History
Date
October 2016
May 2016
May 2016
November 2015
May 2015
December 2014
June 2014
February 2014
December 2013
November 2012
May 2012
January 2012
Altera Corporation
Name
This field can be read and written as a test scratch
register without affecting the reset manager function.
Note that this register is not affected by a warm reset
and can be used for storing pieces of information that
must survive a warm reset.
Version
2016.10.28 Maintenance release.
2016.05.27 Maintenance release.
2016.05.03 Maintenance release.
2015.11.02 Updated "Reset Pins" section
2015.05.04 Updated:
• MISC Group, Generated Module Resets table
• "Reset Pins" section
2014.12.15
• Signal power information added to "HPS External Reset Sources"
section
• Updated block diagram with
2014.06.30
• Updated "Functional Description of Reset Manager"
• Added address map and register descriptions
2014.02.28
Updated sections:
• Reset Sequencing
• Warm Reset Assertion Sequence
2013.12.30
Minor formatting issues.
1.2 • Added cold and warm reset timing diagrams.
1.1 Added reset controller, functional description, and address map and
register definitions sections.
1.0 Initial release.
Description
Changes
h2f_dbg_rst_n
cv_5v4
2016.10.28
Access Reset
RW 0x0
signal
Reset Manager
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