Altera cyclone V Technical Reference page 149

4-6
Power Up Phase
passive parallel (FPP) mode. FPGA configuration through the HPS supports all the capabilities of FPP
mode, including the following items:
• FPGA configuration
• Partial FPGA reconfiguration
• FPGA I/O configuration, followed by PCI Express (PCIe
• External single event upset (SEU) scrubbing
• Decompression
• Advanced Encryption Standard (AES) encryption
• FPGA
DCLK
Configuring the FPGA portion of the SoC device comprises the following phases:
1. Power up phase
2. Reset phase
3. Configuration phase
4. Initialization phase
5. User mode
The FPGA Manager can be configured to accept configuration data directly from the MPU or the DMA
engine. Either the processor or the DMA engine moves data from memory to the FPGA Manager data
image register space
necessary to increment the address when writing the image data because all accesses within the 4 KB
image data region will be transferred to the configuration logic.
Related Information
• Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
For more information about configuring the FPGA through the HPS, refer to the "Configuration,
Design Security, and Remote System Upgrade in Cyclone V Devices" appendix in the Cyclone V Device
Handbook Volume 1: Device Interfaces and Integration.
Booting and Configuration
•
Power Up Phase
In this phase, the VCC is ramping up and has yet to reach normal levels. This phase completes when the
on-chip voltage detector determines that the VCC has reached normal levels.
Reset Phase
The FPGA manager resets the FPGA portion of the SoC device when the FPGA configuration signal
( ) is driven low. The HPS configures the FPGA by writing a 1 to the
nCONFIG
register. This action causes the FPGA portion of the device to reset and perform the following actions:
1. Clear the FPGA configuration RAM bits
2. Tri-state all FPGA user I/O pins
3. Pull the
4. Use the FPGA CB to read the values of the
The
nconfigpull
reset phase. Setting the bit releases the FPGA from the reset phase and transitions to the configuration
phase.
Altera Corporation
clock used for initialization phase clock
. The L4 interconnect allocates a 4 KB region for image data. It is not
img_data_w
on page 30-1
and
nSTATUS CONF_DONE
bit of the register needs to be set to 0 when the FPGA has successfully entered the
ctrl
) configuration of the remainder of FPGA
®
pins low
pins to determine the configuration scheme
MSEL
2016.10.28
bit of the
nconfigpull ctrl
FPGA Manager
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