Altera cyclone V Technical Reference page 968

14-22
Load Command Parameters
in the ATA control register), the state machine performs the following actions after receiving the
†
response:
• Does not drive the P-bit; it waits for CCS, decodes and goes back to idle state, and then drives the
†
P-bit.
• If the host wants to send the CCSD command and if eight clock cycles are expired after the response, it
sends the CCSD pattern on the command pin.
Load Command Parameters
Commands or responses are loaded in the command path in the following situations:
• New command from BIU—When the BIU sends a new command to the CIU, the
to 1 in the
• Internally-generated
request is loaded.
• Interrupt request (IRQ) response with relative card address (RCA) 0x000—When the command path is
waiting for an IRQ response from the MMC and a "send irq response" request is signaled by the BIU,
the send IRQ request bit (
Loading a new command from the BIU in the command path depends on the following
†
settings:
•
update_clock_registers_only
only the
cmdarg
•
wait_prvdata_complete
of the following conditions:
• Immediately, if the data path is free (that is, there is no data transfer in progress), or if an
open-ended data transfer is in progress (
• After completion of the current data transfer, if a predefined data transfer is in progress.
Send Command and Receive Response
After a new command is loaded in the command path (the
register is set to 0), the command path state machine sends out a command on the card bus.
Figure 14-6: Command Path State Machine
Altera Corporation
†
register.
cmd
send_auto_stop
†
send_irq_response
, , and
clkena clkdiv clksrc
, and registers. It then processes the new command, which is sent to the card.
tmout
—If this bit is set to 1, the command path loads the new command under one
†
load_new_cmd
response_expected = 0
Transmit
Command
response_expected = 1
†
—When the data path ends, the SD/SDIO STOP command
) is set to 1 in the
—If this bit is set to 1 in the
registers. If this bit is set to 0, the command path loads the
†
= 0).
bytcnt
update_clock_registers_only
†
Command
Idle
Send IRQ
Response
Request
Receive
Response
†
start_cmd
†
register.
ctrl
register, the command path updates
cmd
t Done
NCC
wait_tncc
Response Done/
Response Timeout
cv_5v4
2016.10.28
bit is set
register bit
cmd
,
cmd
†
†
bit in the
cmd
†
SD/MMC Controller
Send Feedback