Altera cyclone V Technical Reference page 631

cv_5v4
2016.10.28
wr_tidemark
Controls the release of the transaction in the write data FIFO.
Module Instance
lwhps2fpgaregs
Offset:
0x5040
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
wr_tidemark Fields
Bit
3:0
level
fn_mod
Sets the block issuing capability to multiple or single outstanding transactions.
Module Instance
lwhps2fpgaregs
Offset:
0x5108
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
HPS-FPGA Bridges
Send Feedback
0xFF400000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Stalls the transaction in the write data FIFO until the
number of occupied slots in the write data FIFO
exceeds the level. Note that the transaction is released
before this level is achieved if the network receives the
WLAST beat or the write FIFO becomes full.
0xFF400000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
wr_tidemark
Register Address
0xFF405040
21 20 19 18
5 4 3 2
RW 0x4
Access
Register Address
0xFF405108
8-49
17 16
1 0
level
Reset
RW 0x4
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