Reset Manager Module Address Map - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Related Information
http://www.altera.com/literature/hb/cyclone-v/hps.html

Reset Manager Module Address Map

Registers in the Reset Manager module
Base Address:
Reset Manager Module
Register
stat on page 3-17
ctrl on page 3-19
counts on page 3-23
mpumodrst on page 3-
24
permodrst on page 3-
25
per2modrst on page 3-
27
brgmodrst on page 3-
29
miscmodrst on page 3-
29
tstscratch
on page 3-31
stat
The STAT register contains bits that indicate the reset source or a timeout event. For reset sources, a field is
1 if its associated reset requester caused the reset. For timeout events, a field is 1 if its associated timeout
occured as part of a hardware sequenced warm/debug reset. Software clears bits by writing them with a
value of 1. Writes to bits with a value of 0 are ignored. After a cold reset is complete, all bits are reset to
their reset value except for the bit(s) that indicate the source of the cold reset. If multiple cold reset
requests overlap with each other, the source de-asserts the request last will be logged. The other reset
request source(s) de-assert the request in the same cycle will also be logged, the rest of the fields are reset
to default value of 0. After a warm reset is complete, the bit(s) that indicate the source of the warm reset
are set to 1. A warm reset doesn't clear any of the bits in the STAT register; these bits must be cleared by
software writing the STAT register. During the boot process, the Boot ROM copies the STAT register value
into memory before clearing it. After booting, you can read the value of the reset status register at memory
address (
r0
Module Instance
rstmgr
Reset Manager
Send Feedback
0xFFD05000
Offset Width Acces
0x0
0x4
0x8
0x10
0x14
0x18
0x1C
0x20
0x54
+ 0x0038).
0xFFD05000
Reset Manager Module Address Map
Reset Value
s
32 RW 0x0
32 RW 0x100000
32 RW 0x80080
32 RW 0x2
32 RW 0x3FFFFFFF
32 RW 0xFF
32 RW 0x7
32 RW 0x0
32 RW 0x0
Base Address
Description
Status Register
Control Register
Reset Cycles Count Register
MPU Module Reset Register
Peripheral Module Reset Register
Peripheral 2 Module Reset
Register
Bridge Module Reset Register
Miscellaneous Module Reset
Register
Test Scratch Register
Register Address
0xFFD05000
Altera Corporation
3-17