Debug Resets - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
ARM Clock Name
TRACECLKIN
Related Information
ARM Infocenter
For more information about the CoreSight port names, refer to the CoreSight Technology System Design
Guide.

Debug Resets

The CoreSight system uses several resets.
Table 10-6: CoreSight Resets
ARM Reset Name
ATRESETn
nCTIRESET
DAPRESETn
PRESETDBGn
HRESETn
PRESETSYSn
nCTMRESET
CoreSight Debug and Trace
Send Feedback
Clock Source
Clock manager
Clock Source
Reset manager
dbg_rst_n
Reset manager
dbg_rst_n
Reset manager
dbg_rst_n
Reset manager
dbg_rst_n
Reset manager
sys_dbg_rst_n
Reset manager
sys_dbg_rst_n
Reset manager
dbg_rst_n
HPS Clock Signal Name
dbg_trace_clk
HPS Reset Signal Name
Debug Resets
Description
TPIU trace clock input. It is
asynchronous to
ATCLK
HPS, this clock can come from
the clock manager or the FPGA
fabric.
Description
Trace bus reset. It resets all
registers in the domain.
ATCLK
CTI reset signal. It resets all
registers in the domain. In
CTICLK
the HPS, there are four instances
of CTI. All four use the same reset
signal.
DAP internal reset. It is connected
to .
PRESETDBGn
Debug APB reset. Resets all
registers clocked by
PCLKDBG
SoC-provided reset signal that
resets all of the AMBA on-chip
interconnect. Use this signal to
reset the DAP AHB-Lite master
port.
Resets system APB slave port of
DAP.
CTM reset signal. It resets all
signals clocked by
CTMCLK
Altera Corporation
10-15
. In the
.
.