Altera cyclone V Technical Reference page 355

cv_5v4
2016.10.28
31 30
15 14
GPLINMUX52 Fields
Bit
0
sel
GPLINMUX53
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 53. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x58C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
System Manager
Send Feedback
29 28 27 26
13 12 11 10
Name
Select source for GPIO/LoanIO 52. 0 : Source for
GPIO/LoanIO 52 is GENERALIO4. 1 : Source for
GPIO/LoanIO 52 is EMACIO18.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
GPLINMUX53
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD0858C
21 20 19 18
5 4 3 2
5-161
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
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