Altera cyclone V Technical Reference page 898

cv_5v4
2016.10.28
re_2_re Fields
Bit
5:0
value
por_reset_count
The number of cycles the controller waits after reset to issue the first RESET command to the device.
Module Instance
nandregs
Offset:
0x2A0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
por_reset_count Fields
Bit
15:0
value
watchdog_reset_count
The number of cycles the controller waits before flagging a watchdog timeout interrupt.
NAND Flash Controller
Send Feedback
Name
Signifies the number of bus interface nand_mp_clk
clocks that should be introduced between read enable
going high to a bank to the read enable going low to
the next bank. The number of clocks is the function of
device parameter Trhz and controller clock frequency.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
The controller waits for this number of cycles before
issuing the first RESET command to the device. The
number in this register is multiplied internally by 16
in the controller to form the final reset wait count.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RW 0x13B
Description
por_reset_count
Access
Register Address
0xFFB802A0
21 20 19 18
5 4 3 2
Access
13-77
Reset
RW 0x32
17 16
1 0
Reset
RW 0x13B
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