Altera cyclone V Technical Reference page 907

13-86
onfi_timing_mode
31 30
15 14
onfi_optional_commands Fields
Bit
15:0
value
onfi_timing_mode
Asynchronous Timing modes supported by the connected ONFI device
Module Instance
nandregs
Offset:
0x3A0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
29 28 27 26
13 12 11 10
Name
The values in the field should be interpreted as
follows[list] [*]Bit 0 - Supports page cache program
command. [*]Bit 1 - Supports read cache commands.
[*]Bit 2 - Supports get and set features. [*]Bit 3 -
Supports read status enhanced commands. [*]Bit 4 -
Supports copyback. [*]Bit 5 - Supports Read Unique
Id. [*]Bit 6 - Supports Change Read Column
Enhanced. [*]Bit 7 - Supports change row address.
[*]Bit 8 - Supports Change small data move. [*]Bit 9 -
Supports RESET Lun. [*]Bit 10-15 - Reserved.[/list]
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RO 0x0
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB803A0
21 20 19 18
5 4 3 2
value
RO 0x0
NAND Flash Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x0
17 16
1 0
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