Altera cyclone V Technical Reference page 940

cv_5v4
2016.10.28
dma_intr_en
Enables corresponding interrupt bit in dma interrupt register
Module Instance
nandregs
Offset:
0x730
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
dma_intr_en Fields
Bit
0
target_error
target_err_addr_lo
Transaction address for which controller initiator interface received an ERROR target response.
Module Instance
nandregs
Offset:
0x740
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
NAND Flash Controller
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0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Controller initiator interface received an ERROR
target response for a transaction.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
dma_intr_en
Register Address
0xFFB80730
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB80740
13-119
17 16
1 0
target_
error
RW 0x0
Reset
RW 0x0
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