Altera cyclone V Technical Reference page 209

Hard processor system
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cv_5v4
2016.10.28
Register
FLASHIO3
on page 5-
120
FLASHIO4
on page 5-
121
FLASHIO5
on page 5-
121
FLASHIO6
on page 5-
122
FLASHIO7
on page 5-
123
FLASHIO8
on page 5-
124
FLASHIO9
on page 5-
124
FLASHIO10
on page 5-
125
FLASHIO11
on page 5-
126
GENERALIO0
on page 5-
127
GENERALIO1
on page 5-
127
GENERALIO2
on page 5-
128
GENERALIO3
on page 5-
129
GENERALIO4
on page 5-
130
GENERALIO5
on page 5-
130
GENERALIO6
on page 5-
131
GENERALIO7
on page 5-
132
GENERALIO8
on page 5-
133
GENERALIO9
on page 5-
133
GENERALIO10
on page
5-134
System Manager
Send Feedback
Offset
Width Acces
s
0x45C
32
RW
0x460
32
RW
0x464
32
RW
0x468
32
RW
0x46C
32
RW
0x470
32
RW
0x474
32
RW
0x478
32
RW
0x47C
32
RW
0x480
32
RW
0x484
32
RW
0x488
32
RW
0x48C
32
RW
0x490
32
RW
0x494
32
RW
0x498
32
RW
0x49C
32
RW
0x4A0
32
RW
0x4A4
32
RW
0x4A8
32
RW
System Manager Module Address Map
Reset Value
sdmmc_d1 Mux Selection
0x0
Register
sdmmc_d4 Mux Selection
0x0
Register
sdmmc_d5 Mux Selection
0x0
Register
sdmmc_d6 Mux Selection
0x0
Register
sdmmc_d7 Mux Selection
0x0
Register
sdmmc_clk_in Mux Selection
0x0
Register
sdmmc_clk Mux Selection
0x0
Register
sdmmc_d2 Mux Selection
0x0
Register
sdmmc_d3 Mux Selection
0x0
Register
trace_clk Mux Selection Register
0x0
trace_d0 Mux Selection Register
0x0
trace_d1 Mux Selection Register
0x0
trace_d2 Mux Selection Register
0x0
trace_d3 Mux Selection Register
0x0
trace_d4 Mux Selection Register
0x0
trace_d5 Mux Selection Register
0x0
trace_d6 Mux Selection Register
0x0
trace_d7 Mux Selection Register
0x0
spim0_clk Mux Selection Register
0x0
spim0_mosi Mux Selection
0x0
Register
5-15
Description
Altera Corporation

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