Altera cyclone V Technical Reference page 281

cv_5v4
2016.10.28
Bit
4
wrfifoinjd
3
wrfifoinjs
2
eccbufinjd
1
eccbufinjs
0
en
qspi
This register is used to enable ECC on the QSPI RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
Module Instance
sysmgr
Offset:
0x168
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
System Manager
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Name
Changing this bit from zero to one injects a double,
non-correctable error into the NAND WRFIFO
RAM. This only injects one double bit error into the
NAND WRFIFO RAM.
Changing this bit from zero to one injects a single,
correctable error into the NAND WRFIFO RAM.
This only injects one error into the NAND WRFIFO
RAM.
Changing this bit from zero to one injects a double,
non-correctable error into the NAND ECCBUFFER
RAM. This only injects one double bit error into the
NAND ECCBUFFER RAM.
Changing this bit from zero to one injects a single,
correctable error into the NAND ECCBUFFER RAM.
This only injects one error into the NAND
ECCBUFFER RAM.
Enable ECC for NAND RAM
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Access
Register Address
0xFFD08168
21 20 19 18
5 4 3 2
derr serr injd
RW RW RW
0x0 0x0 0x0
5-87
qspi
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
17 16
1 0
injs en
RW RW 0x0
0x0
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