Altera cyclone V Technical Reference page 792

11-54
dramifwidth
dramaddrw Fields
Bit
15:13
csbits
12:10
bankbits
9:5
rowbits
4:0
colbits
dramifwidth
This register controls the interface width of the SDRAM controller.
Module Instance
sdr
Offset:
0x5030
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
This field defines the number of chip select address bits.
Set this field to 0x0 for single chip select and to 0x1 for
two chip selects.
When this field is set to 0x1, you may use rank
interleaved mode by programming the
ctrlcfg.addrorder field to 0x2. If you are using a single
rank memory interface (csbits=0x0), you may not
enable the rank interleaved mode (ctrlcfg.addrorder
must be set less than 0x2).
When this field is set to 0x1 to enable dual ranks, the
chip select (cs) bit of the incoming address is used to
determine which chip select is active. When the chip
select bit of the incoming address is 0, chip select 0
becomes active. When the chip select bit of the
incoming address is 1, chip select 1 becomes active.
The number of bank address bits for the memory
devices in your memory interface.
The number of row address bits for the memory devices
in your memory interface.
The number of column address bits for the memory
devices in your memory interface.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Base Address
0xFFC20000
Access
Register Address
0xFFC25030
SDRAM Controller Subsystem
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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