Altera cyclone V Technical Reference page 265

cv_5v4
2016.10.28
Bit
3:0
arcache_0
USB Controller Group Register Descriptions
Registers related to USB Controllers which aren't located inside the USB controllers themselves.
Offset:
0x118
l3master
on page 5-71
Controls the L3 master HPROT AHB-Lite signal. These register bits should be updated only during system
initialization prior to removing the peripheral from reset. They may not be changed dynamically during
peripheral operation All fields are reset by a cold or warm reset.
l3master
Controls the L3 master HPROT AHB-Lite signal. These register bits should be updated only during system
initialization prior to removing the peripheral from reset. They may not be changed dynamically during
peripheral operation All fields are reset by a cold or warm reset.
System Manager
Send Feedback
Name
Specifies the value of the module ARCACHE signal.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
USB Controller Group Register Descriptions
Description
Description
Noncacheable and nonbufferable.
Bufferable only.
Cacheable, but do not allocate.
Cacheable and bufferable, but do not allocate.
Reserved.
Reserved.
Cacheable write-through, allocate on reads
only.
Cacheable write-back, allocate on reads only.
Reserved.
Reserved.
Cacheable write-through, allocate on writes
only.
Cacheable write-back, allocate on writes only.
Reserved.
Reserved.
Cacheable write-through, allocate on both
reads and writes.
Cacheable write-back, allocate on both reads
and writes.
5-71
Access Reset
RW 0x0
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