Accelerator Coherency Port - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Implementation Details
When the processor writes to any coherent memory location, the SCU ensures that the relevant data is
coherent (updated, tagged or invalidated). Similarly, the SCU monitors read operations from a coherent
memory location. If the required data is already stored within the other processor's L1 cache, the data is
returned directly to the requesting processor. If the data is not in L1 cache, the SCU issues a read to the L2
cache. If the data is not in the L2 cache memory, the read is finally forwarded to main memory. The
primary goal is to maximize overall memory performance and minimize power consumption.
The SCU maintains bidirectional coherency between the L1 data caches belonging to the processors.
When one processor performs a cacheable write, if the same location is cached in the other L1 cache, the
SCU updates it.
Non-coherent data passes through as a standard read or write operation.
The SCU also arbitrates between the Cortex-A9 processors if both attempt simultaneous access to the L2
cache, and manages accesses from the ACP.

Accelerator Coherency Port

The ACP allows master peripherals—including FPGA-based peripherals—to maintain data coherency
with the Cortex-A9 MPCore processors and the SCU. Dedicated master peripherals in the HPS, and those
built in FPGA logic, access the coherent memory through the ACP ID mapper and the ACP.
The ACP port allows one-way coherency. One-way coherency allows an external ACP master to see the
coherent memory of the Cortex-A9 processors but does not allow the Cortex-A9 processors to see
memory changes outside of the cache.
A master on the ACP port can read coherent memory directly from the L1 and L2 caches, but cannot write
directly to the L1 cache. The possible ACP master read and write scenarios are as follows:
• ACP master read with coherent data in the L1 cache: The ACP gets data directly from the L1 cache and
the read is interleaved with a processor access to the L1 cache.
• ACP master read with coherent data in L2 cache: The ACP request is queued in the SCU and the
transaction is sent to the L2 cache.
• ACP master read with coherent data not in L1 or L2 cache: Depending on the previous state of the
data, the L1 or L2 cache may request the data from the L3 system interconnect. The ACP is stalled until
data is available, however ACP support of multiple outstanding transactions minimizes bottlenecks.
• ACP master write with coherent data in the L1 cache: The L1 cache data is marked as invalid in the
Cortex-A9 MPU and the line is evicted from the L1 cache and sent to L2 memory. The ACP write data
is scheduled in the SCU and is eventually written to the L2 cache. Later, when the Cortex-A9 processor
accesses the same memory location, a cache miss in the L1 occurs.
• ACP master write, with coherent data in the L2 cache: The ACP write is scheduled in the SCU and then
is written into the L2 cache.
• ACP master write, with coherent data not in L1 or L2 cache: ACP write is scheduled.
Note: The entire 4 GB address space can be accessed coherently through the ACP through a 1 GB
coherent window implemented through the ACP ID mapper.
Note: Refer to the Cyclone V SoC device errata for details on ARM errata that directly affect the ACP.
Related Information
• ACP ID Mapper
Cortex-A9 Microprocessor Unit Subsystem
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Implementation Details
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