Altera cyclone V Technical Reference page 13

Timer .................................................................................................................23-1
Features of the Timer.................................................................................................................................23-1
Timer Block Diagram and System Integration...................................................................................... 23-1
Functional Description of the Timer.......................................................................................................23-2
Clocks.............................................................................................................................................. 23-3
Resets............................................................................................................................................... 23-3
Interrupts.........................................................................................................................................23-3
FPGA Interface...............................................................................................................................23-3
Timer Programming Model..................................................................................................................... 23-5
Initialization....................................................................................................................................23-5
Enabling the Timer........................................................................................................................ 23-5
Disabling the Timer....................................................................................................................... 23-5
Loading the Timer Countdown Value.........................................................................................23-5
Servicing Interrupts....................................................................................................................... 23-6
Timer Address Map and Register Definitions........................................................................................23-6
Timer Module Address Map.........................................................................................................23-6
Document Revision History...................................................................................................................23-16
Watchdog Timer................................................................................................ 24-1
Features of the Watchdog Timer..............................................................................................................24-1
Watchdog Timer Block Diagram and System Integration................................................................... 24-2
Functional Description of the Watchdog Timer....................................................................................24-2
Watchdog Timer Counter............................................................................................................. 24-2
Watchdog Timer Pause Mode...................................................................................................... 24-3
Watchdog Timer Clocks................................................................................................................24-3
Watchdog Timer Resets.................................................................................................................24-3
FPGA Interface...............................................................................................................................24-4
Watchdog Timer Programming Model...................................................................................................24-4
Setting the Timeout Period Values.............................................................................................. 24-4
Selecting the Output Response Mode......................................................................................... 24-4
Enabling and Initially Starting a Watchdog Timer....................................................................24-5
Reloading a Watchdog Counter................................................................................................... 24-5
Pausing a Watchdog Timer...........................................................................................................24-5
Disabling and Stopping a Watchdog Timer................................................................................24-5
Watchdog Timer State Machine...................................................................................................24-5
Watchdog Timer Address Map and Register Definitions.....................................................................24-7
L4 Watchdog Module Address Map............................................................................................ 24-7
Document Revision History...................................................................................................................24-21
CAN Controller................................................................................................. 25-1
Features of the CAN Controller............................................................................................................... 25-1
CAN Controller Block Diagram and System Integration.....................................................................25-2
Functional Description of the CAN Controller..................................................................................... 25-3
Message Object...............................................................................................................................25-3
Message Interface Registers.......................................................................................................... 25-7
TOC-13
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