Altera cyclone V Technical Reference page 878

cv_5v4
2016.10.28
acc_clks
Timing parameter from read enable going low to capture read data
Module Instance
nandregs
Offset:
0x130
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
acc_clks Fields
Bit
3:0
value
number_of_planes
Number of planes in the device
Module Instance
nandregs
Offset:
0x140
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
NAND Flash Controller
Send Feedback
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Signifies the number of bus interface nand_mp_clk
clock cycles, controller should wait from read enable
going low to sending out a strobe of nand_mp_clk for
capturing of incoming data.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
acc_clks
Register Address
0xFFB80130
21 20 19 18
5 4 3 2
RW 0x0
Access
Register Address
0xFFB80140
13-57
17 16
1 0
value
Reset
RW 0x0
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