Altera Stratix II Reference Manual
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Altera Stratix II Reference Manual

Altera Stratix II Reference Manual

Dsp development board
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Stratix II DSP Development Board
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Reference Manual
Document Version:
Document Date:
6.0.1
August 2006

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Summary of Contents for Altera Stratix II

  • Page 1 Stratix II DSP Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Document Version: 6.0.1 Document Date: August 2006...
  • Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.

  • Page 3: Table Of Contents

    Board Overview ............................. 2–1 Power ..............................2–3 Clocks & Clock Distribution ......................2–4 Board Components ..........................2–7 Stratix II Device (U18) ........................2–7 Switch Inputs ............................ 2–8 Configuration-Status LEDs ......................2–8 Dual Seven-Segment Display & LEDs ..................2–9 A/D Converters ..........................2–10 D/A Converters ..........................
  • Page 4 Contents Chapter 3. Getting Started Using the Board ............................. 3–1 Apply Power ............................. 3–1 Configure the Stratix II Device Directly ..................3–2 Non-Volatile Configuration ......................... 3–2 Configuration Data .......................... 3–3 Factory & User Configurations ...................... 3–4 The Factory Design .......................... 3–5 Install or Remove the Active Heat Sink .....................

  • Page 5: About This Manual

    For technical support or other information about Altera products, go to the Altera world-wide web site at www.altera.com. You can also contact Altera Altera through your local sales representative or any of the sources listed below. Information Type USA & Canada...

  • Page 6: Typographic Conventions

    The warning indicates information that should be read prior to starting or continuing the procedure or processes The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. 2–vi Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 7: Chapter 1. Introduction

    Stratix II EP2S60/EP2S180 device in a 1,020-pin package. The Stratix II DSP development board provides a hardware platform that designers can use to start developing DSP systems based on Stratix II devices. Combined with DSP intellectual property (IP) from Altera and...

  • Page 8: Debugging Interfaces

    Several 0.1-inch headers Expansion Interfaces ■ Two connectors for Analog Devices A/D converter daughter cards ■ Connector for Texas Instruments Evaluation Module (TI-EVM) daughter cards ■ Two Expansion Prototype connectors 1–2 Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 9: Block Diagram

    The Stratix II DSP development board can be damaged without proper anti-static handling. The DSP Development Kit, Stratix II Edition includes a heat sink and fan combination, also known as an active heat sink. Depending on the specific requirements of your application, this level of cooling may not be necessary.

  • Page 10: Handling The Board

    When handling the board, it is important to observe the following precaution: Board Without proper anti-static handling, you can damage the board. Therefore, use the proper anti-static handling precautions when touching the board. 1–4 Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 11: Chapter 2. Board Components & Interfaces

    BoardDesignFiles directory. Figure 1 shows a top view of the board components and interfaces. Figure 1. Stratix II DSP Development Board Components & Interfaces D/A External Clock Input (J12) 9-Pin RS-232 Connector (J9) External Clock Inputs (J10, J11)
  • Page 12 Board Overview Table 1 describes the components on the board and the interfaces it supports. Table 1. Stratix II DSP Development Board Components & Interfaces (Part 1 of 2) Component/ Board Type Description Interface Designation Components ® FPGA EP2S60/EP2S180 Stratix II device...

  • Page 13: Power

    Board Components & Interfaces Table 1. Stratix II DSP Development Board Components & Interfaces (Part 2 of 2) Component/ Board Type Description Interface Designation VGA D/A Converter One 8-bit, 180 megapixels-per-second triple D/A converter for VGA output Audio CODEC 96-KHz stereo audio CODEC...

  • Page 14: Clocks & Clock Distribution

    Stratix II device pin J14 PROTO1 (J25 pin 11) and PROTO2 (J28 pin 11) via a buffer (U7) pld_CLKIN0,pld_CLKIN1 100-MHz oscillator Stratix II device pins AM17 and A16 pld_CLKIN0_n,pld_CLKIN1_n External CLKIN_n input (J11) Stratix II device pins AL17 and B16 proto1_OSC, proto2_OSC...
  • Page 15 J18 and J19 control which clock is routed to the D/A converters. See Table 14 for details. The Stratix II DSP development board can obtain a clock source from one or more of the following sources: ■ The on-board crystal oscillator ■...
  • Page 16 J10. To use an external clock signal, remove the crystal oscillator from its socket. Make sure to note the correct orientation of the oscillator before removing it. 2–6 Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 17: Board Components

    The Stratix II EP2S180 device on the board features 71,760 adaptive logic modules (ALMs) in a speed grade (-3) 1,020-pin FineLine BGA package. The device has 9,383,040 total RAM bits. For more information on Stratix II devices, refer to the Stratix II Device Handbook. Table 5 describes the features of the Stratix II EP2S60F1020C4 and EP2S180F1020C3 devices.

  • Page 18: Switch Inputs

    LED4 Error If the red Error LED is on, then configuration was not transferred from flash memory into the Stratix II device. This can happen if, for example, the flash memory contains neither a valid user or factory configuration. LED1...

  • Page 19: Dual Seven-Segment Display & Leds

    Dual Seven-Segment Display & LEDs A dual seven-segment display and two LEDs are provided. The segments illuminate if the Stratix II pin to which they are connected drives low. They appear unlit when the connected Stratix II device pin drives high.

  • Page 20: A/D Converters

    HEX_0DP HEX_1D HEX_1DP A/D Converters The Stratix II DSP development board has two 12-bit A/D converters that produce samples at a maximum rate of 125 mega-samples per second (MSPS). The A/D subsystem of the board has the following features: ■...
  • Page 21 A/D converters Table 9. A/D Clock Source Settings J3, J4 Setting Clock Source Signal Name Pins 1 and 2 Stratix II PLL circuitry adc_PLLCLK1, adc_PLLCLK2 Pins 3 and 4 OSC or External input adc_CLK_IN1,...
  • Page 22 Board Components A/D Converter Stratix II Pin-Outs Tables 11 show the ADC A (U1) and ADC B (U2) Stratix II pin-outs. Table 11. ADC A (U1) Stratix II Pin-Outs Signal Name Stratix II Pin adcA_D0 (LSB) adcA_D1 adcA_D2 adcA_D3 adcA_D4...

  • Page 23: D/A Converters

    ■ The analog output from each D/A converter is single-ended The D/A converters expect data in an unsigned integer format. The D/A clock signals are output directly from the Stratix II device to the converters. Figure 4 shows the on-board circuitry after a D/A converter. The output of a D/A converter chip, DAC904, consists of a current source whose maximum value is 20 mA.
  • Page 24 D/A converters. Table 14. D/A Clock Source Settings J18, J19 Setting Clock Source Signal Name Pins 1 and 2 Stratix II PLL Circuitry dac_PLLCLK1, dac_PLLCLK2 Pins 3 and 4 Stratix II PLL Circuitry dac_PLLCLK1_n,...
  • Page 25 Board Components & Interfaces D/A Converter Stratix II Pin-Outs Tables 15 show the DAC A (U14) and DAC B (U15) Stratix II pin-outs. Table 15. D/A A (U14, J15) Stratix II Pin-Outs Signal Name Stratix II Pin dacA_D1 (MSB) dacA_D2...

  • Page 26: Sram Memory (U43 & U44)

    (MSB) and bit 14 as the least significant bit (LSB). SRAM Memory (U43 & U44) U43 and U44 are two 256 Kbyte x 16-bit asynchronous SRAM devices. They are connected to the Stratix II device so they can be used by a ® Nios II embedded processor as general-purpose memory.
  • Page 27 AE20 SE_D6 AB20 SE_D7 AF20 SE_D8 AC21 SE_D9 AD21 SE_D10 AB21 SE_D11 AE21 SE_D12 AG20 SE_D13 AF21 SE_D14 AD22 SE_D15 AF22 SE_D16 AE22 SE_D17 AC17 SE_D18 AE19 SE_D19 AD19 Altera Corporation Reference Manual 2–17 August 2006 Stratix II Development Board...
  • Page 28 SRAM_OE_N AG14 SRAM_WE_N AH14 Table 18 lists the reference information for the SRAM memory. Table 18. SRAM Memory Reference Item Description Board reference U43, U44 Device description SRAM Memory 2–18 Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 29: Flash Memory (U17)

    Board Components & Interfaces Flash Memory (U17) U17 is a 16-Mbyte flash memory device connected to the Stratix II device. It can be used for two purposes: ■ A Nios II embedded processor implemented in the Stratix II device can use the flash as general-purpose readable memory and non-volatile storage.
  • Page 30 AB30 FLASH_A17 AB29 FLASH_A18 FLASH_A19 FLASH_A20 AA30 FLASH_A21 AA29 FLASH_A22 AB32 FLASH_A23 AB31 FLASH_D0 AH30 FLASH_D1 AH29 FLASH_D2 AJ32 FLASH_D3 AJ31 FLASH_D4 AG30 FLASH_D5 AG29 FLASH_D6 AH32 FLASH_D7 AH31 2–20 Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 31: Sdram Memory (U39 & U40)

    The SDRAM is fully synchronous with all signals registered on the positive edge of the system clock. The SDRAM device pins are connected to the Stratix II device. An SDRAM controller peripheral is included with the Stratix II DSP Development Kit, allowing a Nios II processor to view the SDRAM devices as a large, linearly-addressable memory.
  • Page 32 Board Components Table 21. SDRAM Device (U39) Pin-Outs (Part 2 of 3) Pin Name Pin Number Connects to Stratix II Pin AB15 AC16 AB16 AE13 AF11 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 AJ10 DQ17 DQ18 DQ19 DQ20 AF12 DQ21...
  • Page 33 DQM3 RAS_N CAS_N CS_N WE_N AK16 Table 22 lists the Stratix II device pin-outs for SDRAM device U40. Table 22. SDRAM Device (U40) Pin-Outs (Part 1 of 3) Pin Name Pin Number Connects to Stratix II Pin AD11 AD13 AB13...
  • Page 34 Board Components Table 22. SDRAM Device (U40) Pin-Outs (Part 2 of 3) Pin Name Pin Number Connects to Stratix II Pin AG13 AF13 AG15 AL14 AJ14 AJ13 AM14 AL20 AH19 DQ10 AJ19 DQ11 AH20 DQ12 AM21 DQ13 AK21 DQ14 AJ21...

  • Page 35: Ethernet Mac/Phy (U16)

    The LAN91C111 (U16) is a mixed signal analog/digital device that implements protocols at 10 Mbps and 100 Mbps. The control pins of U16 are connected to the Stratix II device so that user logic (e.g., the Nios II processor) can access Ethernet via the RJ-45 connector (RJ1). Refer to Table 24 for Stratix II pin-outs for Ethernet MAC/PHY device U16.t...
  • Page 36 AL23 SE_A16 AL24 SE_A17 AJ25 SE_A18 AH25 SE_A19 AL25 SE_D0 AD18 SE_D1 AB18 SE_D2 AB19 SE_D3 AC20 SE_D4 AD20 SE_D5 AE20 SE_D6 AB20 SE_D7 AF20 SE_D8 AC21 SE_D9 AD21 2–26 Reference Manual Altera Corporation Stratix II Development Board August 2006...
  • Page 37 SE_D29 AD10 SE_D30 AC11 SE_D31 AE11 Table 25 lists the reference information for the Ethernet MAC/PHY. Table 25. Ethernet MAC/PHY Reference Item Description Board reference Device description Ethernet MAC/PHY Altera Corporation Reference Manual 2–27 August 2006 Stratix II Development Board...

  • Page 38: Compactflash Connector (Con1)

    FPGA does not drive this signal directly. Table 26 provides CompactFlash pin-out details. Table 26. CompactFlash (CON1) Pin Table (Part 1 of 3) Pin on CompactFlash CompactFlash Function Connects to (CON1) (U60) CS0# ATA_SEL# AD12 2–28 Reference Manual Altera Corporation Stratix II Development Board August 2006...
  • Page 39 Table 26. CompactFlash (CON1) Pin Table (Part 2 of 3) Pin on CompactFlash CompactFlash Function Connects to (CON1) (U60) IOCS16# CD2# CD1# AC15 CS1# VS1# AB10 IORD# IOWR# INTRQ CSEL# VS2# RESET AE12 WAIT# INPACK# REG# DASP# PDIAG# Altera Corporation Reference Manual 2–29 August 2006 Stratix II Development Board...

  • Page 40: Mictor Connector (J20)

    Most pins on J20 connect to I/O pins on the Stratix II device (U18). For systems that do not use the Mictor connector for debugging the Nios II processor, any on-chip signals can be routed to I/O pins and probed at J20 via a Mictor cable.
  • Page 41 CO MM POW ER Five of the signals connect to both the JTAG pins on the Stratix II device (U18) and the Stratix II device’s JTAG connector (J24). The JTAG signals have special usage requirements. You cannot use J20 and J24 at the same time.

  • Page 42: Vga Interface (J35)

    Table 29. VGA Interface (U45, J35) Pin-Outs (Part 1 of 2) Signal Stratix II Pin vga_B0 vga_B1 vga_B2 vga_B3 vga_B4 vga_B5 vga_B6 vga_B7 vga_G0 vga_G1 vga_G2 vga_G3 vga_G4 vga_G5 vga_G6 2–32 Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 43: Audio Codec (U5)

    The stereo jacks are driven by a Stereo Audio CODEC running at 8-96 KHz. Table 31 shows the pin-outs for the CODEC. Table 31. Audio CODEC (U5) Pin-Outs (Part Signal Stratix II Pin audio_BCLK audio_CS_n Altera Corporation Reference Manual 2–33 August 2006 Stratix II Development Board...

  • Page 44: Expansion Interfaces

    Board reference Device description Stereo Audio CODEC, 8-96 KHz Voltage 3.3 V Expansion The Stratix II DSP development board includes the following interfaces: Interfaces ■ A TI-EVM/FPDP connector (J31, J33), located on the reverse side of the board ■ An RS-232C Serial I/O interface (J29) ■...
  • Page 45 Altera Corporation Reference Manual 2–35 August 2006 Stratix II Development Board...
  • Page 46 2–36 Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 47: Rs-232C Serial I/O Interface

    U58) are used between J29 and the Stratix II device, because the Stratix II device cannot interface to RS-232 voltage levels directly. J29 can transmit all RS-232 signals. The Stratix II design may use only the signals it needs, such as J29’s RXD and TXD. LEDs are connected to the RXD and TXD signals, giving a visual indication when data is being transmitted or received.
  • Page 48 Expansion Interfaces Figure 8. Serial Connector J29 DTR1 RXD1 Function TXD1 DCD1 Direction Stratix II Pin # Connector Pin # Connector Pin # StratixII Pin # Direction CTS1 RTS1 DSR1 Function Table 34 shows the pin-outs for the RS-232C interface.

  • Page 49: Analog Devices Corporation External A/D Support

    Board Components & Interfaces Analog Devices Corporation External A/D Support The Stratix II DSP development board supports Analog Devices A/D converters via two 40-pin 0.1-inch digital I/O headers (J5, J6). These two dual-purpose digital I/O headers can support a maximum of the following three converters.

  • Page 50: Expansion Prototype Connector (J23, J24, J25)

    41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins on the Stratix II device. Each signal passes through analog switches (U19, U20, U21, U22 and U25) to protect the Stratix II device from 5 V logic levels. These analog switches are permanently enabled. The output logic-level on the expansion prototype connector pins is 3.3 V.
  • Page 51 Notes to Figure Unregulated voltage from AC to DC power transformer Clk from board oscillator Clk from the Stratix II device via buffer Clk output from the card to the Stratix II device Altera Corporation Reference Manual 2–41 August 2006...

  • Page 52: Expansion Prototype Connector (J26, J27, J28)

    41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins on the Stratix II device. Each signal passes through analog switches (U27, U28, U29, U30 and U31) to protect the Stratix II device from 5-V logic levels. These analog switches are permanently enabled. The output logic-level on the expansion prototype connector pins is 3.3 V.
  • Page 53 Notes to Figure Unregulated voltage from AC to DC power transformer Clk from board oscillator Clk from the Stratix II device via buffer Clk output from card connected to the Stratix II device. Altera Corporation Reference Manual 2–43 August 2006...
  • Page 54 Expansion Interfaces 2–44 Reference Manual Altera Corporation Stratix II Development Board August 2006...

  • Page 55: Chapter 3. Getting Started

    If configuration is successful, the CONF_DONE LED (LED5) illuminates. If the Stratix II device is programmed with a design in one of the user configuration memory spaces or using the JTAG connector (J21), both the CONF_DONE LED (LED5) and the USER LED (LED1) illuminate.

  • Page 56: Configure The Stratix Ii Device Directly

    (U17) on power-up. Upon power-up, the configuration controller begins reading data from the flash memory. The flash memory, Stratix II device, and configuration controller are connected so that data from the flash configures the Stratix II device in fast passive-parallel mode. 3–2...

  • Page 57: Configuration Data

    Click SOF Data under Input files to convert. Click Add File. Browse to the SOF to convert and click OK. The Quartus II software converts the file and saves the output file to the specified directory. Altera Corporation Reference Manual 3–3 August 2006 Stratix II Development Board...

  • Page 58: Factory & User Configurations

    Stratix II device is programmed with by setting the DIP switches on SW2. DIP switches 1 through 3 on SW2 select one of four possible Stratix II configuration images upon power-up. When DIP switch 4 is in the “OPEN”...

  • Page 59: The Factory Design

    DSP Development Kit, Stratix II Edition Getting Started User Guide. Install or The DSP Development Kit, Stratix II Edition includes a heat sink and fan combination, also known as an active heat sink. This active heat sink Remove the...

  • Page 60: Remove The Active Heat Sink

    Peel off the film covering the thermal tape on the bottom of the heatsink. Center the heat sink on top of the Stratix II FPGA. The active heat sink can be mounted in two directions; mount it so the wires are as close as possible to the J36 connector.

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