Altera cyclone V Technical Reference page 135

3-24
mpumodrst
counts Fields
Bit
27:8
nrstcnt
7:0
warmrstcycles
mpumodrst
The MPUMODRST register is used by software to trigger module resets (individual module reset signals).
Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST
register. It is up to software to ensure module reset signals are asserted for the appropriate length of time
and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that
would prevent software from de-asserting the module reset signal. For example, software should not assert
the module reset to the CPU executing the software. Software writes a bit to 1 to assert the module reset
signal and to 0 to de-assert the module reset signal. All fields except CPU1 are only reset by a cold reset.
The CPU1 field is reset by a cold or warm reset.
Module Instance
rstmgr
Offset:
0x10
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
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Name
The Reset Manager pulls down the nRST pin on a
warm reset for the number of cycles specified in this
register. A value of 0x0 prevents the Reset Manager
from pulling down the nRST pin.
On a warm reset, the Reset Manager releases the reset
to the Clock Manager, and then waits for the number
of cycles specified in this register before releasing the
rest of the hardware controlled resets. Value must be
greater than 16.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
0xFFD05000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Access
Register Address
0xFFD05010
21 20 19 18
5 4 3 2
l2 scupe wds
r
RW RW
0x0 RW 0x0
0x0
cv_5v4
2016.10.28
Reset
RW 0x800
RW 0x80
17 16
1 0
cpu1 cpu0
RW RW 0x0
0x1
Reset Manager
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