Altera cyclone V Technical Reference page 941

13-120
target_err_addr_hi
31 30
15 14
target_err_addr_lo Fields
Bit
15:0
value
target_err_addr_hi
Transaction address for which controller initiator interface received an ERROR target response.
Module Instance
nandregs
Offset:
0x750
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
target_err_addr_hi Fields
Bit
15:0
value
flash_burst_length
Altera Corporation
29 28 27 26
13 12 11 10
Name
Least significant 16 bits
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Most significant 16 bits
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RO 0x0
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RO 0x0
Description
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB80750
21 20 19 18
5 4 3 2
Access
NAND Flash Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x0
17 16
1 0
Reset
RO 0x0
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