System Interconnect Block Diagram And System Integration - Altera cyclone V Technical Reference

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System Interconnect Block Diagram and System Integration

System Interconnect Block Diagram and System Integration
Interconnect Block Diagram
Figure 7-1: L3 Interconnect and L4 Buses
32-Bit APB Bus
(L4_MP, l4_mp_clk)
GPIO
(3)
S
DAP
S M
ETR
M
SD/MMC
S M
EMAC
(2)
S M
USB
OTG
S (2) M
NAND
S M
S
32-Bit AXI
(nand_x_clk)
32-Bit AXI (nand_x_clk)
32-Bit AHB (usb_mp_clk)
32-Bit APB (l4_mp_clk)
S S
32-Bit AHB
Quad SPI
(l4_mp_clk)
Flash
System
Manager
Note: System interconnect slaves are available for connection from peripheral masters. System intercon‐
nect masters connect to peripheral slaves. This terminology is the reverse of conventional
terminology used in Qsys.
Related Information
• Master to Slave Connectivity Matrix
Main Connectivity Matrix
•
System Interconnect Architecture
The L3 interconnect is a partially-connected switch fabric. Not all masters can access all slaves.
Altera Corporation
32-Bit AXI
(cfg_clk)
L3 Interconnect
(NIC-301)
32-Bit AHB (dbg_clk)
L3 Master
32-Bit AXI
Peripheral
(dbg_at_clk)
Switch
S
l3_mp_clk
32-Bit AHB
(l4_mp_clk)
S
32-Bit AXI 32-Bit AXI
(l4_mp_clk) (l3_mp_clk)
S M
32-Bit AHB
(usb_mp_clk)
S
32-Bit AXI
(nand_x_clk)
S
L3 Slave Peripheral Switch
l3_sp_clk
M
M
M
M
M
M
32-Bit APB Bus
(L4_OSC1, osc1_clk)
S S S S
OSC1 Watchdog Clock
Timer (2) (2) Manager Manager
on page 7-3
S
FPGA-to-HPS HPS-to-FPGA
FPGA
Bridge Bridge
Manager
S M S
64-Bit AXI 64-Bit AXI
(l3_main_clk) (l3_main_clk)
M S M
(GPV)
S (GPV)
M
L3 Main Switch (1)
l3_main_clk
(GPV) S
M
S
M
M
M
M S
32-Bit AXI
(l3_sp_clk)
S
M
M
M M
32-Bit APB Bus
(L4_SPI_M, spi_m_clk)
S S S
Reset Scan SPI
Manager Master (2)
on page 7-4
Lightweight
HPS-to-FPGA Bridge
S
(GPV)
32-Bit AXI
(l4_mp_clk)
MPU Subsystem
(mpu_clk)
ACP ID
64-Bit AXI
64-Bit AXI
Mapper
(mpu_l2_ram_clk)
(mpu_l2_ram_clk)
S M
S
64-Bit AXI
(mpu_l2_ram_clk)
32-Bit AXI
(dbg_at_clk)
STM
S
32-Bit AXI
(l3_main_clk)
Boot
S
ROM
64-Bit AXI
(l3_main_clk)
On-Chip
S
RAM
32-Bit AXI (l3_main_clk)
DMA
M
64-Bit AXI
(l4_main_clk)
S
S
32-Bit APB (l4_main_clk)
32-Bit APB Bus
SPI Slave
(L4_MAIN,
(2)
l4_main_clk)
S
32-Bit APB Bus
(L4_SP, I4_sp_clk)
S S S S
2
SP I C UART CAN
Timer (2) (4) (2) (2)
cv_5v4
2016.10.28
Legend
M: Master
S: Slave
Switch Connection
ARM Cortex-A9
MPCore
CPU0 CPU1
SCU
S ACP
M M
64-Bit AXI 64-Bit AXI
(mpu_clk) (mpu_clk)
S S
L2
M
Cache
M
64-Bit AXI
(mpu_l2_ram_clk)
S
SDRAM
S
Controller
Subsystem
S
System Interconnect
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