Altera cyclone V Technical Reference page 844

cv_5v4
2016.10.28
Related Information
Discovery and Initialization
Device Operation Control
This section provides a list of registers that you need to program while choosing to use multi-plane or
cache operations on the device. If the device does not support multi-plane operations or cache operations,
then these registers can be left at their power-on reset values with no impact on the functionality of the
NAND flash controller. Even if the device supports these sequences, the software does not need to use
them. Software can leave these registers at their power-on reset values.
Program the following registers in the
• Set
flag
multi-plane operations to access the data on the flash device connected to the NAND flash controller. If
the flash controller is set up for multi-plane operations, the number of pages to be accessed is always a
multiple of the number of planes in the device.
• If the NAND flash controller is configured for multi-plane operation, and if the device has support for
multi-plane read command sequence, set the
• If the device implements multiplane address restrictions, set the
multiplane_addr_restrict
• Initialize the
• If the device supports cache command sequences, enable the
cache_read_enable
• Clear the
support the copyback command sequences. The register defaults to enabled state.
• The
read_mode
written by software, because the NAND flash controller is capable of using the correct sequences based
on a combination of some multi-plane or cache-related settings of the NAND flash controller and the
manufacturer ID. If at some future time these settings change, program the registers to accommodate
the change.
ECC Enabling
Before you start any data operation on the flash device, you must decide whether you want the ECC
enabled or disabled.
Initialize the memory data before you enable ECC the first time, to prevent spurious ECC.
If the ECC needs enabling, set up the appropriate correction level depending on the page size and the
spare area available on the device.
Set the
flag
following registers in the
• Initialize the
• Program the
software needs to preserve the bad block marker.
Related Information
ECC on page 13-18
NAND Flash Controller
Send Feedback
on page 13-3
bit in the
multiplane_operation
register to 1.
and
die_mask first_block_of_next_plane
registers in the
bit of the
flag copyback_disable
, and
write_mode copyback_mode
bit in the register in the
ecc_enable
group must be programmed accordingly, else they can be ignored:
config
register to the appropriate correction level.
ecc_correction
spare_area_skip_bytes
group to achieve the best performance from a given device:
config
register in the
config
multiplane_read_enable
registers as per device requirements.
group.
config
register in the
config
registers, in the
group to 1 to enable ECC. If enabled, the
config
and
spare_area_marker
Device Operation Control
group to 1 if the device supports
register in the
bit in the
flag
and
cache_write_enable
group to 0 if the device does not
group, currently need not be
config
registers in the
config
13-23
group.
config
group if the
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